FIELD OF THE INVENTION
The invention relates to a microprocessor having a central control unit, a memory of the EEPROM type, and a protective device which assures that during a reading operation in the EEPROM memory, the clock speed of the central control unit will not exceed a limit value at which reading of the memory is reliably assured; wherein the protective device has a clock conditioning unit with a clock input which externally inputs a microprocessor clock and which reduces the microprocessor clock by frequency division during a reading operation of the memory, so that during the reading operation a clock signal having a clock cycle being lengthened as compared with other operations is available for controlling the central control unit; and a linking device having two clock signal inputs and one clock signal output, wherein one clock signal input of the linking device is connected with the clock signal input of the microprocessor, the other clock signal input of the linking device is connected to the clock signal output of the clock conditioning unit, and the clock signal output of the linking device furnishes the clock signal for triggering the central control unit; and wherein the linking device is triggered by the central control unit in such a way that it alternatingly transmits the microprocessor clock applied to the clock signal input and the clock furnished by the clock conditioning unit, to the central control unit.
Such a microprocessor is used especially in security-related systems. That term refers to systems in which the microprocessor must be prevented from detecting a memory cell state that does not match the actual memory contents, in a reading operation of the EEPROM. It applies, for instance, to microprocessors for use in smart cards or chip cards, which are used in credit or debit systems or in entry monitoring systems or access systems.
One microprocessor of that generic type is described in German Published, Non-Prosecuted Application DE 40 29 598 A1. In that microprocessor, within a given period of time, the microprocessor clock signal applied from outside is always applied directly, for a given first time segment, and with a frequency divided by a given value, for a given second time segment, to the central control unit. The sum of the first and second time periods equals the duration of the given period of time. That assures that the mean clock speed will remain constant regardless of a reading operation actually occurring during the given period of time.
German Published, Non-Prosecuted Application DE 38 34 227 A1 also describes a microprocessor with a central control unit and a memory, in which the frequency of the clock signal supplied to the memory is converted to a desired frequency by a divider. However, in that case the frequency of the clock signal supplied to the central control unit is not changed.
The reading operation of typical semiconductor memories of the EEPROM type requires a certain minimum amount of time. Secure, unequivocal readout of the contents of typical EEPROMs can be performed, at the fastest, within a period of time that corresponds to a clock speed of the central unit or CPU doing the reading, or approximately 10 MHz. If the CPU is operated at a higher clock speed, then it always reads the same binary value out of the EEPROM, that is either ones or zeros only.
When EEPROM-type memories are used in microprocessors made by N-MOS technology, that is not a problem, because the CPU in such processors can be operated at a maximum clock speed of approximately 6 MHz, for example. Modern microprocessors, however, especially if made by CMOS technology, can be operated at a CPU clock speed of up to 30 MHz.
If a memory of the EEPROM type is used in such a processor, then the processor, given secure reading of the memory contents, cannot be operated at such a high clock speed. Yet it cannot be precluded that someone might operate such a microprocessor without authorization at a high enough clock speed or frequency that unequivocal reading of the memory content of the EEPROM by the CPU is the result.